Panmnesia Moves to Mass-Produce World’s First CXL 3.2 Switch with Port-Based Routing
Event summary
- Panmnesia will mass-produce its PCIe 6.4-CXL 3.2 fusion fabric switch in H2 2026, the only silicon fully implementing CXL 3.2 including Port-Based Routing (PBR).
- The chip supports both PCIe and CXL protocols on a single die, enabling flexible device connectivity in AI data centers and HPC environments.
- Key differentiators include PBR support for direct peer-to-peer communication, switch cascading for large-scale fabrics, and proprietary ultra-low-latency controller technology.
The big picture
Panmnesia’s mass production of a CXL 3.2 switch with Port-Based Routing addresses growing demand for flexible, high-performance interconnect solutions in AI data centers. The technology enables composable architectures at rack scale, reducing resource waste and operational costs for large language models and scientific simulations. This move positions Panmnesia as a key player in the evolving AI infrastructure landscape.
What we're watching
- Adoption Pace
- How quickly early access partners integrate the switch into AI data centers and HPC environments.
- Competitive Response
- Whether competitors can match Panmnesia’s PBR implementation or proprietary controller technology.
- Market Impact
- The extent to which the switch reduces CAPEX and OPEX in large-scale AI workloads, influencing data center architecture trends.
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