Everspin's CXL-MRAM Breakthrough Solves the AI Memory Bottleneck

CHANDLER, AZ – September 29, 2026 – For years, enterprise data center architects have chased the holy grail of memory: a tier that operates with the blistering speed of traditional RAM but retains its data when the power is pulled, all without the crutch of external batteries. At the SNIA Developer Conference (SDC) 2026, Everspin Technologies, a manufacturer of Magnetoresistive RAM (MRAM), demonstrated a proof-of-concept that might finally deliver on that promise and fundamentally alter the economics of AI infrastructure.

The company unveiled what it reports as the world’s first Compute Express Link (CXL)-connected MRAM platform. By mating its PERSYST MRAM with standard CXL connectivity, the hardware developer has effectively inserted a high-speed, non-volatile memory tier directly between volatile DRAM and slower NAND flash storage. The working system—powered by a Supermicro AS-1116CS-TN server, an AMD EPYC 9355 32-core processor, and an AMD Alveo U250 FPGA running a Wolley CXL controller—promises cache-line-level, nanosecond-class access times. Furthermore, the demonstrated write speeds are up to 100 times faster than those of traditional NAND-based solid-state storage.

“Everspin has been working with data center customers for 15 years, and we continue to innovate as AI changes the memory needs of systems,” said Sanjeev Aggarwal, president and CEO of Everspin Technologies. “CXL gives us a standard way to bring persistent MRAM to a much broader range of compute platforms. We now have a working system so customers can run their own workloads and measure the benefit for their specific applications.”

Solving the AI Checkpoint Bottleneck

The timing of this demonstration is no coincidence. The generative AI boom has pushed existing compute infrastructures to their absolute limits, exposing critical bottlenecks in how systems handle vast amounts of memory-resident data. Modern AI clusters, particularly those tasked with training massive Large Language Models (LLMs), suffer from a phenomenon known as the "memory wall."

During frequent training checkpoints—where the system must save the current state of the model to prevent catastrophic data loss in the event of a crash—expensive GPU clusters are often forced to sit idle while data is flushed to slower storage drives. At upwards of $30,000 per high-end AI accelerator, having a cluster of thousands of GPUs waiting on storage I/O is a catastrophic waste of capital expenditure.

By introducing a CXL-connected MRAM tier, infrastructure engineers can preserve state instantaneously. Because MRAM is inherently non-volatile and operates at near-DRAM speeds, the checkpointing process no longer requires stalling the GPU cluster. Data is simply written to the MRAM buffer, where it remains safe regardless of power fluctuations. Furthermore, this architecture creates new opportunities for persistent key-value (KV) caches, which are crucial for high-concurrency and low-latency AI inference. CXL facilitates memory pooling and sharing across multiple hosts, allowing persistent memory capacity to be dynamically allocated exactly where workloads need it most.

Beyond Optane: Resurrecting Persistent Memory

The quest for a viable Storage Class Memory (SCM) tier is not new. For years, Intel championed this space with its Optane technology, which promised similar benefits but ultimately faltered due to proprietary lock-in, high costs, and scaling challenges. When Intel officially wound down its Optane business, it left a significant vacuum in the enterprise hardware ecosystem.

Everspin’s approach represents a vendor-agnostic second chance for non-volatile tiering. By leveraging Compute Express Link—an open industry standard protocol designed to enable high-speed, low-latency connections between CPUs, GPUs, and memory—the new platform bypasses the proprietary interconnect limitations that doomed earlier attempts.

“Wolley enables memory and storage connectivity through CXL, and this demonstration with Everspin shows how persistent MRAM can be brought into that environment with memory semantics,” noted Dr. Bernard Shung, CEO of Wolley, in the official announcement. “Together, we are demonstrating a practical way to connect persistent memory through CXL and make it available to today’s compute platforms.”

However, the commercial viability of this resurrection hinges heavily on density and cost-per-gigabyte. The SDC demonstration utilized 1GB DDR4 MRAM UDIMMs. While perfectly adequate for a proof-of-concept, scaling these densities to meet the multi-terabyte requirements of modern data centers presents a formidable manufacturing challenge. MRAM fabrication requires highly specialized annealing processes and magnetic field exposure. Current industry estimates place MRAM manufacturing yields between 70% and 85%, noticeably trailing the 90-plus percent yields of mature NAND flash processes.

The supply chain dynamics here are complex. While the manufacturer recently secured a $40 million contract with a major U.S. defense contractor and inked a ten-year agreement with Microchip Technology to expand on-shore manufacturing for its PERSYST line, true enterprise scale requires massive volume. Overcoming these economic hurdles will be critical if this technology is to move from specialized mission-critical deployments into mainstream hyperscale adoption.

The End of Battery-Backed DRAM

Beyond the raw performance metrics, the integration of persistent MRAM over CXL offers a profound operational advantage: the potential eradication of battery-backed DRAM and supercapacitors from the data center floor.

Historically, to ensure data survival during sudden power-loss events, enterprise facilities have relied on volatile DRAM paired with bulky battery backup units (BBUs) or supercapacitors. When power fails, these batteries provide just enough juice to flush the data from the DRAM into a non-volatile NAND SSD. Data center operations engineers have long viewed these battery-backed Non-Volatile Dual In-line Memory Modules (NVDIMMs) as a necessary evil. They are a notorious point of failure in an ecosystem that demands "five nines" (99.999%) of uptime. Batteries degrade over time, require regular replacement, and introduce significant environmental and fire-safety liabilities.

The inherent non-volatility of Magnetoresistive RAM eliminates this precarious dance entirely. Data written to an MRAM module persists across power interruptions natively, without relying on a battery or necessitating a panic-flush to an SSD. This "instant-on" capability drastically simplifies failover design and cuts ongoing maintenance costs.

For data center facility managers focused on greening their operations, the removal of toxic battery backups and the reduction in standby power consumption represent a massive leap forward. MRAM boasts virtually unlimited write endurance—enduring up to 10¹⁵ write/erase cycles compared to NAND's 3,000 to 100,000—and can retain data for over two decades without power.

The Ecosystem and the Road Ahead

While the Arizona-based manufacturer is pioneering this specific intersection of technologies, it is not operating in a vacuum. The broader memory industry is rapidly coalescing around the CXL standard as the definitive answer to AI's escalating memory demands. Competitors are aggressively developing CXL compute accelerators, while the SNIA MRAM Alliance Special Interest Group (SIG)—launched earlier this year—is actively working to standardize MRAM interfaces across LPDDR, CXL, and chiplet architectures.

This collective industry momentum suggests that the hardware demonstrated at SDC 2026 is merely the opening salvo in a much larger architectural shift. As AI workloads continue to pivot from initial training phases toward widespread, real-time inferencing, the demand for low-latency access to vast pools of memory-resident data will only intensify.

Industry analysts tracking early-stage enterprise infrastructure note that while alternative non-volatile technologies like ReRAM and FRAM offer their own distinct advantages, MRAM's unique combination of CMOS process compatibility, extreme endurance, and radiation tolerance makes it uniquely suited for the rigors of modern AI and mission-critical edge computing. The true test over the next 18 to 24 months will be whether fabrication yields can improve enough to drive down the cost-per-gigabyte, allowing this high-performance tier to scale beyond niche deployments and into the sprawling racks of the world's largest cloud providers.