DVCon U.S. 2026 Shatters Records as AI Dominates Verification Talks

SANTA CLARA, CA – March 19, 2026 – The Design and Verification Conference and Exhibition U.S. (DVCon U.S.) 2026 has concluded with record-breaking attendance and a resounding focus on Artificial Intelligence as the industry's next frontier in tackling the ever-growing complexity of chip design. Held at a new, larger venue in Santa Clara, the Accellera Systems Initiative-sponsored event drew 1,243 professionals from across the globe, solidifying its position as the premier forum for the electronic design and verification community.

The conference, which ran earlier this month, was marked by packed technical sessions, a vibrant exhibition floor, and a palpable buzz around AI's potential to finally break the notorious "verification bottleneck." The week's highlights included keynotes from leaders at Siemens, Micron, and NVIDIA, a spirited panel debate on AI's role, and the recognition of outstanding technical contributions through the annual Stuart Sutherland Best Paper and Best Poster awards.

AI Takes Center Stage in Tackling the 'Verification Bottleneck'

A dominant theme throughout DVCon U.S. 2026 was the urgent need for new methodologies to address the verification bottleneck, a challenge that consumes an estimated 68% of the total chip development cycle. This "Verification Productivity Gap 2.0," as some in the industry call it, is being exacerbated by the rise of complex chiplet-based systems, 3D-ICs, and software-defined hardware, making traditional verification methods increasingly unsustainable.

The conference agenda directly confronted this issue. The Tuesday industry keynote, “Beyond Bigger Designs: Rethinking Verification for the Era of Convergence,” delivered by executives from Siemens EDA and Micron Technology, set the tone. The speakers argued that the focus of verification must shift from simply managing design size to handling the intricate interactions between hardware, software, and system-level workloads.

This conversation culminated in Wednesday's lively panel discussion, “Is AI the Key to Ending the Verification Bottleneck?” Moderated by Vishal Karna of Qualcomm Technologies, the session featured a diverse group of experts from NVIDIA, Synopsys, Altera, Cadence Design Systems, and even AI research leader OpenAI. The panelists engaged in a spirited debate on the promise versus the practical realities of applying AI, concluding with a broad consensus that AI will indeed play a significant and transformative role in relieving the industry's most persistent headache.

Further reinforcing the theme, Stuart Oberman, Vice President of GPU Hardware Engineering at NVIDIA, delivered a compelling keynote titled “From Pixels to Tokens: Chip Design and Verification in the Era of AI.” Drawing on decades of GPU innovation, Oberman emphasized that AI is no longer a futuristic concept but an essential tool for managing the complexity and accelerating the pace of modern SoC development. He highlighted the emergence of AI-driven and agentic workflows as critical for scaling design and verification for the next generation of silicon. The third-place Best Paper award also went to a team from NVIDIA for their work on an LLM-driven debugging assistant for formal verification failures, showcasing a practical application of these advanced concepts.

Record Growth and a Strategic Move to Santa Clara

The conference's success was not just thematic but also quantitative. Overall attendance soared to 1,243, a significant 17% increase from the previous year's record. This figure included 598 first-time attendees, signaling a strong influx of new talent and interest in the field. This growth is part of a sustained upward trend, with attendance consistently climbing since the event returned to an in-person format.

Fueling this expansion was the strategic relocation to the Hyatt Regency in Santa Clara. The move provided much-needed space for the growing event, allowing for an exhibition floor that was at capacity with 34 sponsors and exhibitors, including five first-timers. The new venue, situated in the heart of Silicon Valley, enhances accessibility for the dense ecosystem of semiconductor and technology companies in the region.

“I am thrilled with the success of DVCon U.S. 2026,” said Xiaolin Chen, the conference's General Chair. “Technical sessions were exceptionally well attended, and the exhibition floor was vibrant with discussion as attendees connected with colleagues and explored the latest innovations in design and verification... With our new Santa Clara venue providing additional space to grow, DVCon continues to expand as the industry’s premier forum for sharing ideas, advancing methodologies, and strengthening the design and verification community.”

The event's global reach was also evident, with participants hailing from 29 countries and representing approximately 350 different companies, underscoring DVCon's international importance as a central meeting point for the industry.

Highlighting Innovation Through Technical Awards

Beyond the high-level discussions on AI, DVCon U.S. celebrated the practical, on-the-ground innovations that drive the industry forward. The prestigious Stuart Sutherland Best Paper Presentation award, voted on by attendees, was presented to Matthew Ballance of AMD for his paper, “Properly Introducing Python to Your UVM Testbench.” The work provides crucial guidance on integrating the popular and versatile Python programming language into the standard Universal Verification Methodology (UVM) framework, a topic of immense practical interest as teams seek more efficient ways to build complex testbenches.

Top honors for the Best Poster went to Bryan Morris and Michael Silveira of Ciena Corp for their poster, “plusargs++: Make Plusargs Great … Like They Never Were Before.” Their work offers an enhanced approach to using plusargs, the command-line arguments that control simulation behavior, promising more flexible and powerful verification environments.

This year also marked the debut of the DVCon U.S. Hackathon. Sponsored by QuickSilicon, the online challenge invited attendees to test their skills on real-world verification problems. Rafid Ahmed Jukaku claimed first place, demonstrating remarkable skill by achieving a perfect score in just 1 hour and 21 minutes, setting a high bar for the new competition.

As the industry looks ahead, the momentum from this year's conference is set to continue. Xiaolin Chen will return as General Chair for DVCon U.S. 2027, which will be held from March 1-4 at the same Santa Clara venue. The proceedings from the 2026 conference are scheduled to be made publicly available on the Accellera archives site in June, allowing the insights and innovations shared to reach an even wider audience.