Breker Taps RISC-V Veteran to Tackle Verification Challenge

SAN JOSE, CA – March 05, 2026 – Breker Verification Systems has appointed Larry Lapides, a renowned RISC-V industry expert and former Synopsys executive, to its Advisory Board. The move is being interpreted by industry watchers as a significant strategic maneuver aimed at solidifying leadership in the complex and rapidly expanding field of RISC-V processor verification.

While personnel announcements are common, this appointment underscores a critical juncture for the open-standard RISC-V architecture. As its adoption accelerates from academic projects to complex, high-performance commercial systems-on-chip (SoCs), the challenge of ensuring these designs are correct and bug-free has become a paramount concern. David Kelf, Breker’s CEO, highlighted the strategic value of the appointment, noting that Lapides has been a “tireless advocate for the adoption of RISC-V processors and the urgent need for RISC-V processor verification tool standards.” Kelf added, “Larry’s RISC-V knowledge and his ties to the RISC-V community are welcome additions to Breker and our advisory board.”

The Verification Imperative in a Customizable World

The core appeal of the RISC-V instruction set architecture (ISA) is its open and extensible nature. Unlike proprietary architectures, RISC-V allows designers to add custom instructions and extensions, tailoring processors for specific workloads in applications ranging from embedded controllers to data center accelerators. However, this flexibility, a key driver of its popularity, is also its greatest verification challenge.

Traditional verification methodologies often struggle with this level of customization. Every new instruction or architectural modification introduces the potential for new bugs and unforeseen interactions at the system level. Verifying a single, standard processor core is a monumental task; verifying a multitude of unique, customized RISC-V cores and ensuring their correct interaction within a complex SoC presents an exponential increase in complexity. Key technical hurdles include ensuring cache coherency across multiple cores, validating complex system-level interactions, and securing the design against potential vulnerabilities introduced by custom logic. The absence of a single “golden” reference model for every possible configuration further complicates the process, making it difficult to definitively prove correctness.

This verification gap is widely seen as a potential brake on RISC-V's growth. Without robust, scalable, and standardized verification solutions, the risk of costly silicon failures and security flaws could deter wider adoption in mission-critical applications.

A Strategic Play for Methodological Leadership

Breker Verification Systems has positioned itself to address this specific challenge. The company is a leading proponent of the Accellera Portable Stimulus Standard (PSS), a methodology designed to create abstract, reusable test scenarios that can be deployed across various verification platforms, from early-stage simulation to post-silicon validation. This approach is particularly well-suited to the RISC-V landscape.

Instead of writing low-level tests for a specific core configuration, PSS allows engineers to define high-level test intent—such as “stress the memory subsystem” or “test security features under load.” Breker’s tools, including its SystemVIP library for RISC-V, then automatically generate the specific, complex test sequences needed to fulfill that intent for a given design. This automation and portability are critical for efficiently verifying the vast array of possible RISC-V implementations. By focusing on system-level scenarios, Breker’s methodology aims to uncover the kinds of complex, architectural bugs that traditional block-level verification might miss. The appointment of Lapides is a clear signal that Breker intends to double down on this strategy, leveraging its PSS expertise to become the de facto leader in verification methodology for the RISC-V ecosystem.

An Architect of Influence Joins the Board

Larry Lapides is not merely an experienced executive; he is a figure whose career traces the evolution of modern electronic design automation (EDA). With over 30 years in the industry, his background provides a unique perspective on the challenges at hand. His time at Verisity Design, a pioneer in advanced functional verification, gave him a deep grounding in the principles of creating robust and reusable test environments.

More recently, his roles at Imperas Software and Synopsys placed him at the very center of the RISC-V movement. At Imperas, he was integral to promoting the virtual prototypes and reference models that are essential for early software development and verification. At Synopsys, as Executive Director of RISC-V Tools Business Development, he was responsible for shaping the strategy of one of the world's largest EDA companies in this emerging market. Throughout these roles, he has been a consistent and vocal advocate for developing a complete and robust ecosystem around RISC-V, with a particular emphasis on the need for mature verification tools and standards. His decision to join Breker's advisory board lends significant weight and credibility to the company's mission.

“Breker sits at the forefront in the development of commercial processor verification solutions and is a valued member of the RISC-V community,” Lapides stated. “It will be a pleasure to work with Breker to move this important effort forward.”

Broader Implications for the RISC-V Ecosystem

The strategic alignment of Lapides' advocacy for standards with Breker's PSS-centric technology could have ripple effects across the industry. This move is more than a simple corporate appointment; it is a powerful endorsement of a specific methodological approach to solving one of the RISC-V community's most pressing problems. By bringing such a prominent RISC-V figure into its inner circle, Breker not only enhances its own strategic direction but also raises the profile of PSS as a key enabling technology for the entire ecosystem.

This development is likely to increase competitive pressure on other EDA vendors to bolster their own system-level and PSS-based verification offerings for RISC-V. Furthermore, the collaboration could help accelerate the formalization of verification standards within organizations like RISC-V International, providing designers with a clearer, more reliable path to verifying their custom processors. For the RISC-V ecosystem, which is striving to transition from a promising alternative to a mainstream staple of the semiconductor industry, establishing this kind of robust verification infrastructure is not just an advantage—it is an absolute necessity.