Synopsys Boosts AI Chip Verification with Software-Defined Hardware Platforms
Event summary
- Synopsys introduced software-defined hardware-assisted verification (HAV) platforms on March 11, 2026, aiming to accelerate AI silicon innovation.
- New HAPS-200 12 FPGA and ZeBu-200 12 FPGA platforms offer up to 2x performance and capacity boosts for AI-era mega designs.
- Industry-first hardware-assisted test automation capabilities enable earlier detection of subsystem-level bugs.
- Synopsys collaborates with AMD and NVIDIA to optimize verification solutions for complex AI platforms.
The big picture
Synopsys' new HAV platforms address the escalating complexity of AI chip verification, driven by rapidly growing large language models and edge AI architectures. The software-defined approach positions Synopsys to support the industry's demand for first-time-right silicon and seamless integration of heterogeneous AI systems. The collaboration with AMD and NVIDIA underscores the strategic importance of these advancements in the AI hardware ecosystem.
What we're watching
- Performance Scaling
- How Synopsys' software-defined approach will sustain performance gains for AI chip verification.
- Market Adoption
- Whether AI chip developers will widely adopt Synopsys' new HAV platforms to meet aggressive timelines.
- Competitive Dynamics
- The pace at which competitors respond with similar verification solutions for AI silicon.
Related topics