Panmnesia Unveils World’s First PCIe 6.4-CXL 3.2 Fusion Switch with Port-Based Routing — Panmnesia, Inc.

Event summary

Panmnesia will supply sample chips of its PCIe 6.4-CXL 3.2 fusion switch in the second half of 2026.
The chip is the world’s only ASIC switch with full CXL 3.2 compliance, including Port-Based Routing (PBR).
Supports both PCIe and CXL protocols on a single die, enabling composable architecture at rack scale.
Key differentiators include ultra-low-latency controller, switch cascading for large-scale fabrics, and direct peer-to-peer communication.

The big picture

Panmnesia’s PCIe 6.4-CXL 3.2 fusion switch addresses the growing need for flexible, high-performance interconnects in AI data centers. As enterprises scale large language models and other AI workloads, the ability to pool and allocate resources dynamically becomes critical. The switch’s support for Port-Based Routing (PBR) and full CXL 3.2 compliance positions it as a potential disruptor in the AI infrastructure space, challenging traditional tree-based architectures.

What we're watching

Adoption Pace: How quickly early access partners integrate the switch into AI data centers and HPC environments.
Competitive Response: Whether established players like Intel or emerging competitors develop comparable PBR-capable switches.
Market Differentiation: The extent to which Panmnesia’s proprietary controller and IP can sustain a performance-per-dollar advantage.