Cadence Expands ChipStack AI with RTL Generation Agent for PPA Optimization
Event summary
- Cadence introduced a new RTL Generation Agent for its ChipStack AI Super Agent, automating front-end digital design and verification.
- The agent delivers 24% area reduction and 18% power reduction versus pure foundation model code generation.
- Honda R&D is evaluating the agent for advanced automotive SoCs, aiming to improve productivity in RTL development.
- The expanded capabilities are expected to be available to select early-access customers in Q4 2026.
The big picture
Cadence is extending its leadership in AI-driven chip design with agentic workflows that automate RTL generation and PPA optimization. This move aligns with broader industry trends toward AI-assisted engineering, particularly in high-performance digital design. The collaboration with Honda underscores the strategic importance of optimizing SoCs for automotive applications, where power and cost constraints are critical.
What we're watching
- Adoption Pace
- The pace at which early-access customers integrate the RTL Generation Agent into their workflows will indicate its real-world utility.
- Competitive Response
- Whether competitors like Synopsys or Siemens EDA will accelerate their own AI-driven design solutions in response.
- PPA Gains
- How sustained the 24% area and 18% power reductions prove to be as more customers deploy the agent.
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