Cadence Achieves First-Pass PCIe 6.0 Compliance with TSMC N3 Implementation
Event summary
- Cadence's PHY and controller IP for PCIe 6.0, implemented in TSMC's N3 process, achieved first-pass compliance at the PCI-SIG workshop in late July 2026.
- The x8 subsystem solution was tested at the full PCIe 6.0 specification speed of 64 GT/s.
- Cadence's solution is now listed on PCI-SIG’s Integrators List.
- Positron AI has licensed Cadence’s SerDes IP for PCIe 6.0 for its AI inference accelerator chip.
The big picture
Cadence's achievement underscores the growing demand for high-bandwidth connectivity in AI and high-performance computing systems. The PCIe 6.0 standard is critical for data center and AI infrastructure, with broader deployment expected in automotive and enterprise systems as the ecosystem matures. This milestone highlights the importance of rigorous compliance and interoperability testing in advancing PCIe technology architecture.
What we're watching
- Adoption Pace
- How quickly PCIe 6.0 technology will be adopted in AI and high-performance computing systems.
- Ecosystem Collaboration
- Whether early ecosystem collaboration will accelerate the deployment of PCIe 6.0 technology.
- Competitive Positioning
- The pace at which Cadence can maintain its competitive edge in the PCIe technology market.
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