Alchip and Synopsys Tackle AI Data Center Bandwidth Bottlenecks with 224G PHY IP Collaboration
Event summary
- Alchip and Synopsys presented a technical paper at the TSMC 2026 North America OIP Ecosystem Forum on September 23, 2026.
- The collaboration combines Synopsys' 224G PHY IP with Alchip's advanced packaging and signal integrity expertise.
- The joint effort addresses die-edge congestion, escape routing complexity, and power integrity constraints in AI data center ASICs.
- The methodology achieved chip-to-chip interconnect bandwidth density approaching theoretical physical limits.
- The approach is protocol-agnostic and forward-scalable, potentially supporting future 448G SerDes implementations.
The big picture
As AI accelerators demand ever-increasing performance, bandwidth constraints have become a critical bottleneck in data center design. This collaboration between Alchip and Synopsys represents an industry-wide push to overcome physical limitations in chip-to-chip communication, which directly impacts system throughput and scalability. The protocol-agnostic approach suggests potential for broader adoption across different networking standards, positioning this solution as a potential foundation for next-generation AI infrastructure.
What we're watching
- Technical Feasibility
- Whether the collaboration's methodology can sustain 1.6 Tbps networking bandwidth in production environments.
- Market Adoption
- The pace at which AI data center operators will integrate this bandwidth-optimized ASIC design.
- Competitive Positioning
- How this collaboration affects Alchip's standing against other ASIC providers in the AI infrastructure space.
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