Advantest Expands SiConic Ecosystem into DFT Engineering — Advantest America, Inc.

Event summary

Advantest extended its SiConic ecosystem to include a Design-for-Test (DFT) Engineering environment on July 16, 2026.
The new environment integrates DFT execution and debug functionality for production-aligned workflows.
SiConic D200 digital instrument supports data rates up to 200 Mbps with low-jitter clock sources.
Availability of the DFT Engineering solution is scheduled for September 30, 2026.

The big picture

Advantest's expansion into DFT Engineering addresses growing complexity in semiconductor testing, particularly for advanced-node SoCs and AI accelerators. By aligning bench-level development with production workflows, the company aims to reduce bottlenecks and improve first-pass success rates in manufacturing. This move reflects broader industry trends toward automation and integration in semiconductor test solutions.

What we're watching

Adoption Pace: How quickly semiconductor manufacturers will integrate the new DFT Engineering solution into their workflows.
Competitive Response: Whether competitors like Teradyne or Keysight Systems will introduce similar bench-level DFT solutions.
Execution Risk: The pace at which Advantest can scale the SiConic ecosystem across multiple engineering communities while maintaining integration with production test platforms.