M31 Unlocks 2nm Era with TSMC, Tapes Out Key IP for AI & Mobile

HSINCHU, Taiwan – April 23, 2026 – In a move that signals the growing maturity of the 2-nanometer semiconductor ecosystem, global IP provider M31 Technology today announced the successful tapeout of its eUSB2V2 interface IP on TSMC's cutting-edge N2P process. The milestone, unveiled at the TSMC 2026 North America Technology Symposium, represents a critical building block that will enable the world's leading chip designers to harness the power of next-generation manufacturing for future artificial intelligence, high-performance computing (HPC), and mobile devices.

The successful tapeout is more than a technical achievement; it is a vital de-risking event for an industry grappling with the immense complexity and cost of designing chips at the atomic scale. By providing a validated, high-performance, and power-efficient interface, M31 and TSMC are paving a smoother path for tech giants to bring their most ambitious designs to life.

The 2nm Frontier and the IP Imperative

TSMC's N2P process represents a monumental leap in semiconductor technology. As an advanced version of the foundational N2 node which entered production in late 2025, it utilizes a new transistor architecture known as nanosheet Gate-All-Around (GAA). This shift from the long-standing FinFET structure is essential for pushing performance boundaries, promising a 10-15% speed boost or a 25-30% power reduction compared to the previous 3nm generation. For chipmakers, these gains are the fuel for the next wave of innovation.

However, harnessing this potential is fraught with challenges. Designing a System-on-Chip (SoC) for a 2nm node is an incredibly complex and resource-intensive endeavor. This is where the role of silicon intellectual property (IP) becomes paramount. IP cores are pre-designed, pre-verified functional blocks—like engines, transmissions, and electronics in a car—that chip designers can license and integrate into their larger SoC designs. Without a robust library of proven IP, each company would have to design every single component from scratch, a process that would be prohibitively expensive, time-consuming, and risky.

M31's eUSB2V2 tapeout provides one of the first and most essential of these building blocks for the N2P platform. It gives companies like Apple, Qualcomm, Nvidia, and MediaTek—all expected to be early adopters of TSMC's 2nm technology for their flagship processors—the confidence to move forward. This validated IP significantly shortens design cycles and allows their engineering teams to focus on their unique, value-adding architectures rather than reinventing foundational interfaces.

Engineering a Legacy Standard for the Future

While the industry buzzes with ever-faster standards, the choice to perfect an eUSB2V2 (USB 2.0 compatible) interface for the world's most advanced process node may seem counterintuitive. The reality, however, is a testament to brilliant engineering focused on real-world needs. For the vast majority of peripheral and internal communication tasks within an SoC, raw multi-gigabit speed is less important than power efficiency, minimal chip area, and broad compatibility. The USB 2.0 ecosystem is ubiquitous, and ensuring a low-power, robust implementation remains a top priority for SoC architects.

The challenge M31 overcame was not inventing a new standard, but re-engineering a proven one to perform flawlessly under the extreme physical constraints and low-voltage requirements of the 2nm node. The resulting eUSB2V2 IP is a masterclass in Power, Performance, and Area (PPA) optimization. It supports data rates up to 4.8 Gbps while operating at low voltages of 1.2V/0.9V, achieving a target power consumption of just 50 milliwatts in standard mode—a critical metric for battery-powered mobile devices and power-hungry AI accelerators.

Furthermore, maintaining signal integrity on infinitesimally small and densely packed wires is a major hurdle at this scale. M31's IP addresses this directly by incorporating an advanced analog front end with programmable features like transmit de-emphasis and receiver equalization. These functions act like sophisticated signal conditioners, ensuring data is transmitted and received without errors, thereby enhancing channel robustness and giving designers much-needed flexibility.

A Blueprint for Collaboration in the Nanosheet Era

The successful tapeout is also a story about the deeply symbiotic relationship required between foundries and IP providers to conquer the frontiers of physics. This achievement was not developed in a vacuum; it was born from a deep, multi-year collaboration between M31 and TSMC. M31, a member of the TSMC Open Innovation Platform (OIP) IP Alliance since 2012 and a seven-time recipient of its Partner of the Year award, worked in lockstep with the foundry giant.

This partnership involved aligning on platform design methodologies, meticulously tuning circuits and physical layouts for the specific electrical characteristics of the N2P process, and validating the IP within TSMC's own reference flows. This level of integration ensures that when a customer licenses the IP, it integrates seamlessly into their design, saving months of costly and frustrating verification work.

"Optimization of IP on advanced process platform is critical to design efficiency and time-to-market," M31 CEO Scott Chang stated in the announcement. He emphasized that this milestone reflects a platform-driven approach that "helps customers integrate this critical interface more efficiently, streamlines the path from design execution to production readiness, and drives competitiveness at the 2 nm node."

This model of deep collaboration is the blueprint for success in the nanosheet era. As manufacturing complexity soars, no single company can master every aspect of chip creation. Foundries like TSMC rely on partners like M31 to build out a rich, reliable ecosystem that makes their advanced manufacturing capabilities accessible and economically viable for their customers.

Paving the Way for Next-Generation Devices

In the fierce race for semiconductor leadership, where TSMC competes with rivals like Intel and Samsung, a mature and ready IP ecosystem is a powerful competitive advantage. This tapeout serves as a strong proof point for the readiness of TSMC's N2P platform, attracting high-volume customers who need to plan their product roadmaps years in advance. Already, major players are committing; MediaTek has publicly announced it is developing a flagship SoC on TSMC's 2nm technology, with volume production expected in late 2026.

By providing this foundational USB IP, M31 is directly enabling the development of these future products. The low-power, high-performance connectivity is ideal for the next generation of smartphone chipsets, AI edge computing devices, and the massive SoCs used in data centers for HPC workloads. The availability of such validated IP is a green light for the industry, signaling that the transition to the 2nm node is not just a theoretical possibility, but a practical reality. This single milestone helps accelerate the entire technology lifecycle, setting the stage for the next wave of devices that will define the digital world.