IBM Shatters Scaling Limits with Sub-1nm Chip, Redefining Computing

YORKTOWN HEIGHTS, N.Y. – June 25, 2026 – International Business Machines today announced a seminal breakthrough in semiconductor technology, unveiling the world's first chip with features smaller than one nanometer. The demonstration of a 0.7-nanometer (nm) node—also measured as 7 angstroms—represents a monumental leap for an industry that has long confronted the physical limits of miniaturization. By packing nearly 100 billion transistors onto a chip the size of a fingernail, IBM has provided a powerful counter-narrative to the slowing of Moore's Law and laid a potential blueprint for the next decade of computational progress.

This achievement, born from the company's research labs in Albany, New York, is not merely an incremental step. It is built on a fundamentally new transistor architecture called "nanostack." This 3D design moves beyond the planar and fin-based structures that have defined chipmaking for decades, vertically stacking and staggering transistors to achieve unprecedented density. The implications are profound, promising to supercharge everything from generative AI and cloud infrastructure to the next wave of consumer electronics.

"IBM's latest chip breakthrough marks a landmark moment in computing, pushing technology beyond the nanometer era to the scale of atoms," said Jay Gambetta, Director of IBM Research and IBM Fellow. "With our new nanostack architecture, we're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency."

The 'Nanostack' Blueprint: Engineering in the Angstrom Era

The core innovation enabling this leap is the nanostack architecture, a three-dimensional design that represents a significant evolution from the Gate-All-Around (GAA) nanosheet technology currently being adopted by industry leaders for their 2nm and 3nm nodes. Where traditional scaling focused on shrinking components on a two-dimensional plane, and GAA wrapped a gate around the transistor channel for better control, nanostack builds upward. It leverages 3D sequential integration to stack transistors on top of one another, nearly doubling the density of IBM's own 2nm chip, which was unveiled in 2021.

This vertical approach does more than just save space. It allows for the use of different material combinations within each stacked layer, enabling engineers to optimize the performance and power characteristics of individual transistors independently. According to technical results presented at the 2026 VLSI Symposium, this architecture has been experimentally validated, confirming it can be physically built and can support real computation. Researchers demonstrated functional CMOS inverters with expected switching performance, a key proof point for any new logic technology.

Furthermore, IBM detailed a 40 percent scaling improvement in SRAM (Static Random-Access Memory) using the nanostack design. As memory density is often a limiting factor in chip design, particularly for the high-bandwidth demands of advanced AI, this finding is a critical validation of the architecture's practical benefits. It signals a path to creating far more efficient and capable chips that can keep pace with the data-hungry workloads of the future.

Supercharging AI and Cloud with Atomic-Scale Efficiency

The tangible impact of this breakthrough is best understood through its projected performance gains. IBM reports the new chip could deliver up to 50 percent more performance at the same power level or a staggering 70 percent greater energy efficiency compared to its 2nm node technology. For a world increasingly reliant on power-hungry data centers and AI models, these figures are transformative.

For the burgeoning field of generative AI, such improvements are a lifeline. The massive computational cost of training and running large language models has created an energy consumption crisis for the tech industry. A 70 percent jump in efficiency could drastically reduce the operational costs and carbon footprint of AI infrastructure, enabling the development of even more powerful and complex models without overwhelming power grids. The increased transistor density and improved SRAM scaling directly address the processing and memory bottlenecks that currently constrain AI development.

In cloud computing, the benefits are equally compelling. More efficient and powerful processors mean data centers can deliver more computational power per rack, reducing physical footprint and cooling requirements. For businesses and consumers, this translates to faster, more responsive cloud services and applications. For mobile and edge devices, the energy savings could usher in a new era of battery life, enabling complex AI tasks to run locally on a device for days, not hours, while making devices themselves smaller and more powerful.

A High-Stakes Race for Semiconductor Supremacy

While IBM's 0.7nm demonstration places it at the bleeding edge of semiconductor research, the path from a lab-validated chip to mass production is a long and arduous one. The company projects a potential production timeline of five years, placing commercial availability around 2031. This timeline highlights the immense challenge of manufacturing at atomic scales.

Production will depend on the maturation of High Numerical Aperture Extreme Ultraviolet (High NA EUV) lithography, the next-generation tool from Dutch giant ASML required to print such infinitesimally small circuits. IBM and its partners, including Lam Research and Tokyo Electron, are working to develop the processes for these tools at the Albany research facility, but the technology is still in its infancy industry-wide.

Meanwhile, the world's leading foundries are on aggressive roadmaps of their own. TSMC, which began volume production of its 2nm node in late 2025, is targeting its 1.6nm (A16) node for late 2026 or 2027. Intel is ramping its 18A (1.8nm class) process, and Samsung is aiming for 1.4nm mass production by 2027. While these nodes use different naming conventions and architectures, the race is on. IBM's role has historically been that of a technology pioneer, developing foundational IP and then partnering with foundries for mass production, a model it is pursuing with Japan's Rapidus for 2nm manufacturing. How this new 0.7nm technology will be commercialized remains a key strategic question.

A Strategic Play for American Tech Leadership

This breakthrough is more than a technical achievement; it's a strategic statement. Coming at a time of intense geopolitical competition over technology supply chains, IBM's work at its Albany hub reinforces the United States' position at the forefront of fundamental R&D. This research, conducted in partnership with a consortium of industry players, is exactly the kind of ecosystem the U.S. government aims to foster through initiatives like the CHIPS and Science Act.

IBM's broader strategy appears to be one of doubling down on deep-tech innovation. The sub-1nm announcement follows its plan to form Anderon, the world's first pure-play quantum foundry, another move designed to secure U.S. leadership in a critical future technology. The expertise gained in advanced materials, fabrication, and process control for the nanostack chip will undoubtedly create synergies with the complex manufacturing required for quantum processors.

By demonstrating a viable path to scaling for another decade, IBM has not only reasserted its legacy of innovation but has also provided a crucial dose of optimism for an industry grappling with fundamental physical barriers. The journey from today's 7-angstrom demonstration to a world powered by these atomic-scale engines will be complex, but the blueprint for the next era of computing has now been drawn.