Ditching the DSP: TeraSignal's Analog Play to Solve AI's Power Crisis

IRVINE, Calif. – September 16, 2026 – In the high-stakes arms race of artificial intelligence, the true battleground is no longer just the compute power of the GPU. It is the thermodynamic reality of moving data. When TeraSignal introduced its Analog Wave Processor (AWP) today, the broader market saw a new high-speed signal-processing architecture. But for those analyzing the underlying signals of data center infrastructure, this announcement represents a targeted strike against the physical and thermal limits of modern AI networks. It is a strategic maneuver designed to unseat the digital monopolies that have long dominated high-speed connectivity.

As AI clusters scale toward 1.6T and 3.2T systems, the industry is slamming into a power wall. For years, the default engineering maneuver has been to rely on power-hungry Digital Signal Processors (DSPs) to clean up degraded signals. TeraSignal is proposing a radical realignment: ditching the digital conversion entirely and performing mathematical operations directly on broadband electrical waveforms.

The Thermodynamic Wall and the DSP Dilemma

To understand the gravity of TeraSignal’s play, we must first look at the crisis brewing inside hyperscale data centers. The transition from 100G per lane to 200G per lane has placed optical and copper interconnects under severe thermal stress. Operating PAM4 signals at 200 Gbps requires a symbol rate of roughly 106 to 112 Gbaud. At these ultra-high frequencies, physical channel impairments escalate non-linearly, with standard PCB traces exhibiting attenuation exceeding -30 dB over modest distances.

The incumbent solution, championed by semiconductor giants like Broadcom and Marvell, relies on brute-force digital processing. These traditional DSPs, built on leading-edge 5nm and 3nm nodes, are incredibly effective but come with a staggering thermodynamic cost. A standard 1.6T retimed optical transceiver dissipates between 20 and 25 watts. The DSP alone consumes up to 2.2 watts per lane, accounting for roughly 70 percent of the module’s entire thermal load.

Across a cluster of 100,000 GPUs, optical interconnects can account for up to 20 percent of the facility's total power draw. Hyperscalers simply cannot scale this architecture indefinitely without melting the rack. The power required to move the data is beginning to cannibalize the power available to compute the data.

Analog Wave Processing: A Forensic Look at the Tech

TeraSignal’s maneuver is classic asymmetric warfare. Rather than competing with the giants on 3nm digital scaling, they are changing the physics of the battlefield. The newly announced AWP architecture implements continuous-time analog mathematical operations—weighting, delay, and accumulation—directly on broadband waveforms.

"Linear connectivity dramatically reduces power and latency, but scaling it to 200G per lane and beyond requires greater visibility into the channel and more powerful ways to correct impairments," said Armond Hairapetian, CEO of TeraSignal. "TSLink tells us what is happening in the link. AWP gives us the ability to correct it. Together, they bring intelligence and advanced signal processing to linear interconnects without the power and latency of a conventional DSP."

The forensic brilliance here lies in what the architecture omits. By eliminating high-rate multi-gigasample ADCs, digital equalization pipelines, and DACs, AWP slashes signal processing power overhead by more than 70 percent. The technology is integrated into TeraSignal’s new Lotus 200G-per-lane product family, which includes the TS5802 copper redriver, the TS8802 linear MZM driver, and the TS9802 linear Transimpedance Amplifier (TIA).

The numbers are striking. A full 1.6T Linear Pluggable Optics (LPO) module built with Lotus-class analog components operates within 7.5 to 9.5 watts, effectively cutting the transceiver thermal load in half compared to full-retimed DSP modules. Furthermore, because operations take place strictly in the continuous-time analog domain without clock domain crossing or digitization pipelines, latency is reduced to sub-nanosecond levels (less than 100 picoseconds per hop), compared to the 100 to 250 nanoseconds introduced by traditional DSPs. In massive scale-up GPU fabrics running collective operations, shaving microseconds off end-to-end communication directly accelerates GPU execution pipelines.

Standardizing the Rebellion: CMIS-LT and TSLink

If analog processing is so efficient, why hasn't it conquered the data center already? The historical barrier to pure linear optics has always been interoperability. In standard LPO, removing the DSP stripped away the diagnostic telemetry and automatic adaptation. If a switch ASIC from one vendor plugged into an optical module from another, the link frequently failed to initialize due to mismatched equalization presets. Pure LPO was a brittle, unmanageable lab experiment.

This is where TeraSignal’s strategic timing becomes evident. The company is pairing AWP with its proprietary TSLink telemetry engine, designed specifically to operate over the newly ratified Optical Internetworking Forum (OIF) CMIS Out-of-Band Link Training (CMIS-LT) standard.

This creates an intelligent, closed-loop feedback system. The host ASIC sends test waveforms, and the TeraSignal components use embedded Digital Eye Monitoring to evaluate the signal in real-time. Through CMIS-LT registers, the module requests adjustments to the host transmitter's feed-forward equalization taps while adapting its own internal AWP delay stages. It brings digital-grade plug-and-play reliability to an analog circuit. At ECOC 2026 in Málaga, Spain, TeraSignal is proving this exact capability in live, multi-vendor interoperability demonstrations at the OIF booth, validating host-to-module link training across heterogeneous switch silicon and optical assemblies.

The Hyperscaler Chessboard

To truly decode the impact of the AWP architecture, we must analyze the intent of the ultimate buyers: the hyperscalers. The market is currently bifurcating into scale-up fabrics (accelerator-to-accelerator) and scale-out fabrics (pod-to-pod).

Meta has been a relentless champion of LPO and Co-Packaged Optics (CPO). Their Open Rack scale-up designs are hitting severe thermal ceilings, and Meta engineers have actively advocated for linear drive solutions and out-of-band link training to replace DSPs in rack-level GPU interlinks. TeraSignal’s architecture is perfectly aligned with Meta’s long-term infrastructure intent.

Microsoft has historically been more conservative, viewing pure LPO with skepticism due to field serviceability and diagnostic blind spots. However, at 200G per lane, the power consumption of standard Active Electrical Cables (AECs) is becoming prohibitive. Microsoft is now actively testing CMIS-LT-enabled active copper cables and half-retimed linear receive optics. A telemetry-rich analog solution like AWP provides the operational compromise Microsoft requires: analog power savings with digital manageability.

Meanwhile, NVIDIA continues to dominate the AI landscape with its vertically integrated NVLink compute trays, heavily utilizing low-power copper interconnects inside a walled garden. For merchant Ethernet silicon vendors who must compete with NVIDIA’s proprietary scale-up fabrics, TeraSignal’s standardized AWP provides critical ammunition. It allows the open Ethernet ecosystem to deliver the low-power, low-latency performance of a vertically integrated system without locking customers into a single vendor.

The DSP is not dead. For long-reach optical runs across data center campuses, the chromatic dispersion of fiber will continue to strictly mandate high-precision digital MLSD engines. But inside the rack, where the battle for AI supremacy is actually being fought, the thermodynamic realities are forcing a strategic realignment. TeraSignal has read the underlying signals of the market perfectly. By combining the raw efficiency of wave-domain processing with the standardized intelligence of closed-loop telemetry, they are not just introducing a new processor; they are rewriting the rules of engagement for the 1.6T era.