Accellera Releases PSS 3.1 to Tackle Heterogeneous SoC Verification Complexity

ELK GROVE, Calif. – Nov. 11, 2026 – The semiconductor industry is facing an unprecedented verification crisis. As modern System-on-Chip (SoC) architectures evolve into deeply intertwined ecosystems of heterogeneous processors, AI accelerators, and complex software stacks, the traditional methods of validating these designs are breaking under the strain. Ensuring that hardware and software interact flawlessly before a multi-million dollar chip goes to manufacturing is no longer just an engineering hurdle; it is a critical business imperative.

Addressing this escalating challenge, the Accellera Systems Initiative—an independent, not-for-profit organization driving electronic design automation (EDA) standards—announced today the board approval and immediate availability of the Portable Test and Stimulus Standard (PSS) 3.1. Building upon the foundational behavioral coverage introduced in PSS 3.0, this latest iteration aggressively expands verification reuse across both hardware and software domains, offering a lifeline to engineering teams drowning in heterogeneous computing complexity.

Bridging the Silicon-Software Divide

The core dilemma in modern chip design is the siloed nature of development. Hardware engineers and software developers often operate in parallel universes, using different tools, languages, and methodologies. When these worlds finally collide during system integration, the resulting bugs are notoriously difficult to isolate and devastatingly expensive to fix.

PSS 3.1 directly targets this silicon-software divide by introducing robust multi-domain coordination features tailored for heterogeneous computing. The standard now includes advanced capabilities for executor grouping, inter-executor communication, and precise synchronization mechanisms. This allows verification teams to explicitly model shared memory regions and coordinate complex behaviors across multiple, distinct processing units.

Furthermore, the 3.1 release dramatically strengthens software integration. By supporting exported functions, the verification environment can now directly interact with a PSS test—for instance, to seamlessly trigger and handle hardware interrupts within a software-driven testbench. Improved template processing and new execution tags that eliminate redundant generated code further streamline the realization of target implementations.

"PSS 3.1 delivers some of the most significant language and methodology enhancements since the introduction of PSS 3.0," said Matthew Ballance, Chair of Accellera's Portable Stimulus Working Group. "The new release provides engineers with more expressive constraint capabilities, greater flexibility in building reusable verification models, improved integration with software-driven environments, and new mechanisms for coordinating verification activity across multiple execution domains."

From IP to Post-Silicon: Maximizing ROI Through Modular Reuse

Verification routinely consumes over half of a semiconductor project's total development time and budget. Historically, this inefficiency stems from redundant effort: engineers write one set of tests for early-stage simulation, entirely different tests for hardware emulation and FPGA prototyping, and yet another suite for post-silicon validation in the physical lab.

PSS 3.1 champions the "write once, run anywhere" paradigm, promising massive returns on investment (ROI) by enabling true modular verification reuse. The new standard introduces highly expressive constraint modeling, including generic constraints that function similarly to reusable programming functions, soft constraints, and enhanced array-slice operations. These additions allow verification intent to be expressed with unprecedented flexibility, drastically reducing model duplication.

Moreover, the standard expands customization through component subtype action overriding, mutable attributes, and instance-qualified references. This means a verification library created for a foundational Intellectual Property (IP) block can be easily adapted and reused as that IP is integrated into a larger, complex SoC, without rewriting the underlying test scenarios. To further support modern memory architectures, the release also strengthens address and register abstraction with support for shared address claims, negative address offsets, and extensible memory-access controls.

"Accellera brings the industry together to develop standards that enable innovation, interoperability, and greater productivity in electronic design and verification," stated Lu Dai, Accellera Chair. "PSS 3.1 extends the value of verification intent through greater reuse, enhanced software integration, and improved support for today’s increasingly complex computing architectures."

Navigating the Transition and Ecosystem Readiness

Despite the clear operational advantages, transitioning to the Portable Stimulus Standard has historically presented adoption barriers. For verification engineers deeply entrenched in the Universal Verification Methodology (UVM) and SystemVerilog, adopting PSS requires learning a new Domain-Specific Language (DSL) or C++ input formats. This learning curve has occasionally slowed widespread implementation, forcing teams to weigh the immediate cost of retraining against long-term efficiency gains.

However, industry analysts view PSS 3.1 as a pivotal usability bridge. While technically a "minor" release compared to its predecessor, its focus on refining existing constructs, removing modeling ambiguities, and simplifying complex scenarios significantly lowers the barrier to entry. To further aid this transition, Accellera continues to invest heavily in educational infrastructure, offering comprehensive resources like a 16-part video series and active community forums to guide engineering teams through the nuances of the standard.

The standard is backed by global EDA heavyweights, including Cadence, Siemens, and Synopsys. While commercial tool vendors tightly guard their specific integration roadmaps, their active sponsorship indicates that native support for PSS 3.1 features will rapidly permeate the commercial EDA ecosystem.

According to a verification director at a leading fabless semiconductor firm, speaking on the condition of anonymity, the initial friction of adopting PSS is quickly offset by downstream savings. The director noted that while rewriting legacy UVM sequences requires an upfront investment, the automated test generation and seamless cross-platform portability provided by PSS ultimately prevent the catastrophic schedule slips caused by late-stage, post-silicon bugs.

Future-Proofing with Shift-Left and AI Integration

The release of PSS 3.1 arrives at a critical juncture for the semiconductor industry, aligning perfectly with the overarching trend of "shift-left" verification. By enabling the reuse of verification intent from the earliest stages of abstract modeling down to physical silicon, PSS allows teams to identify and resolve critical architectural flaws months before a chip is manufactured.

Furthermore, the standard's structured approach to verification intent positions it as a vital enabler for the next frontier of electronic design: Artificial Intelligence. As the EDA industry aggressively integrates machine learning to automate chip design, these AI-driven tools require clean, standardized, and machine-readable data inputs to generate intelligent test scenarios. The highly structured, implementation-independent models created using PSS 3.1 provide exactly the framework necessary to feed future AI verification engines.

Coupled with Accellera's recent release of the Functional Safety Language (FSL) 1.0 standard, it is evident that the organization is systematically building a comprehensive, interoperable ecosystem for the next generation of electronics. As software-defined vehicles, hyperscale data centers, and edge AI devices continue to push the boundaries of silicon complexity, the ability to predictably, efficiently, and portably verify these systems will remain the defining competitive advantage for the industry's top players.