IBM and Lam Research Extend Semiconductor Scaling Collaboration to Sub-1nm Nodes
Event summary
- IBM and Lam Research have signed a five-year agreement to develop sub-1nm logic scaling technologies.
- The collaboration focuses on novel materials, advanced etch/deposition processes, and High NA EUV lithography.
- IBM's Albany NanoTech Complex and Lam's process tools will be used to validate full process flows for nanosheet and nanostack devices.
- The partnership builds on over a decade of collaboration, including work on 7nm, nanosheet, and EUV process technologies.
The big picture
This collaboration underscores the industry's push toward sub-1nm logic scaling, critical for AI and next-generation computing. The partnership leverages Lam Research's process tools and IBM's research capabilities to address the technical hurdles of 3D scaling and High NA EUV lithography. Success could redefine the boundaries of semiconductor performance and power efficiency.
What we're watching
- Technical Feasibility
- Whether IBM and Lam Research can overcome the challenges of High NA EUV lithography for sub-1nm nodes.
- Industry Adoption
- The pace at which the developed technologies will be integrated into commercial semiconductor production.
- Competitive Positioning
- How this collaboration affects the competitive landscape for advanced semiconductor manufacturing.
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