JEDEC Solid State Technology Association

JEDEC Solid State Technology Association is a global leader in developing open standards for the microelectronics industry. Headquartered in Arlington, Virginia, its mission is to serve the solid-state industry by creating, publishing, and promoting global acceptance of standards, while also providing a forum for technical exchange on leading industry topics. [1, 5, 8, 13, 17, 19]

The association's key activities involve the standardization of various microelectronic components and technologies. This includes memory devices such as DDR SDRAM, LPDDR, and DDR5, as well as interfaces, component packaging, test methods, quality and reliability, thermal standardization, electronic sensitivity, electrical interfaces, and wide bandgap technologies. JEDEC publishes numerous standards, publications, and registration outlines annually, facilitating universal compatibility and reducing development costs across the semiconductor industry. [1, 5, 13, 14, 15, 20]

In recent news, JEDEC announced significant advancements in April 2026, including milestones for the DDR5 multiplexed rank data buffer (MDB) standard and progress on the multiplexed rank registering clock driver (MRCD) standard. The organization is also actively developing the DDR5 MRDIMM Gen2 roadmap to enable higher-bandwidth memory designs. Furthermore, JEDEC previewed its LPDDR6 roadmap, which includes new features and an LPDDR6-based SOCAMM2 specification, specifically addressing the growing demands of AI memory. The association regularly hosts forums focused on next-generation memory for AI, server, cloud, and mobile computing. [2, 4, 5, 6, 9]

Latest updates

JEDEC Accelerates DDR5 Memory Roadmap with New Standards

Event summary

  • JEDEC published JESD82-552 (DDR5MDB02) for multiplexed rank data buffers.
  • JEDEC anticipates the release of JESD82-542 (DDR5MRCD02) for registering clock drivers soon.
  • The MRDIMM Gen2 standard is nearing completion, targeting 12,800 MT/s data rates.
  • Development is underway for Gen2 DDR5 MRDIMM raw card designs and the MRDIMM Gen3 standard.

The big picture

JEDEC's advancements in DDR5 MRDIMM technology are directly tied to the escalating bandwidth demands of AI, cloud computing, and enterprise workloads. These standards are essential for enabling higher-performance memory modules, but their success hinges on the ability of manufacturers to meet aggressive data rate targets and the willingness of key infrastructure providers to adopt the new designs. The ongoing development of Gen3 MRDIMM standards signals a commitment to continued innovation in memory technology.

What we're watching

Technical Feasibility
The successful integration of the new data buffer and clock driver standards will be crucial for achieving the targeted 12,800 MT/s data rates, and any delays could impact the adoption of Gen2 MRDIMM designs.
Competitive Landscape
The pace at which competing memory technologies, such as LPDDR6, evolve will influence the long-term relevance and market share of DDR5 MRDIMM solutions.
Adoption Rate
How quickly server and cloud computing infrastructure providers adopt these new standards will dictate the overall demand and revenue potential for DDR5 MRDIMM manufacturers.
CID: 2856