Park Systems' Strategic Leap: Alliance with imec to Master 3D Chip Metrology

GWACHEON, South Korea – June 10, 2026 – In a move that underscores the critical link between measurement and manufacturing innovation, nanometrology leader Park Systems has announced a two-year joint development program (JDP) with imec, the world-renowned semiconductor research hub. The partnership aims to develop the advanced metrology solutions required for the next generation of 3D advanced packaging and logic chips—the very technologies that will define the future of computing.

This strategic alliance is not just a technical collaboration; it's a calculated move by Park Systems to solidify its leadership in a high-stakes, high-growth segment of the semiconductor industry. Timed to coincide with the inauguration of its new global headquarters in Gwacheon, the JDP signals a company leveling up its ambitions, moving from a specialized leader in atomic force microscopy (AFM) to a comprehensive solutions provider for the industry's most complex challenges. For business leaders and investors, this partnership offers a clear window into the foundational technologies that will enable future growth and competitive advantage in the tech sector.

The Vertical Frontier: Navigating the Complexities of 3D Chips

For decades, the semiconductor industry has been propelled by Moore's Law, the relentless shrinking of transistors on a two-dimensional plane. But as physical limits approach, the path forward is increasingly vertical. The industry is pivoting to 3D advanced packaging and novel transistor architectures, stacking components and building circuits in three dimensions to boost performance, reduce power consumption, and overcome the "memory wall"—the bottleneck created by the distance between processing and memory.

This shift to 3D integration, however, introduces a dizzying array of manufacturing complexities. We're no longer just etching flat surfaces. We're building microscopic skyscrapers. Technologies like die-to-wafer hybrid bonding, with interconnect pitches shrinking towards an astonishing 200 nanometers, and new transistor designs like Gate-All-Around (GAA) nanosheets demand unprecedented precision. A single, sub-nanometer flaw in a through-silicon via (TSV) or a hidden defect beneath a bonded layer can render an entire multi-chip package useless.

This is where metrology—the science of measurement—transforms from a quality control step into a strategic enabler. "Future semiconductor architectures and materials introduce significant new challenges for device integration, and even more so for metrology," states Philippe Leray, Vice President R&D for Patterning at imec. Without the ability to precisely measure and inspect these intricate 3D structures at every stage of production, the industry's roadmap to future nodes like the 2 Ångström (A2) generation would grind to a halt.

A Multi-Modal Arsenal for Nanoscale Inspection

Recognizing that no single tool can solve these multifaceted challenges, the JDP will deploy Park Systems' full suite of metrology solutions. This multi-modal approach is the core of the strategy, combining different technologies to create a complete picture of the device.

At the heart of the portfolio is Park Systems' foundational expertise in Atomic Force Microscopy (AFM). Born from the work of its founder, Dr. Sang-il Park, at Stanford, AFM provides unparalleled high-resolution 3D imaging, capable of measuring the surface roughness and critical dimensions of the most advanced GAA transistors with atomic-level precision. It’s the final arbiter of nanoscale accuracy.

However, AFM can be slow for inspecting large areas. To address this, the portfolio includes faster, optical-based technologies. White Light Interferometry (WLI) provides rapid, non-contact 3D surface mapping, crucial for inspecting the height and flatness of micro-bumps and ensuring the perfect alignment needed for wafer-level bonding. Digital Holographic Microscopy (DHM) offers similar high-speed topographical data, with the added ability to potentially see through transparent layers to detect subsurface defects.

Complementing these topographical tools is Imaging Spectroscopic Ellipsometry (ISE), which measures the thickness and optical properties of the countless thin films that make up a modern chip. In complex 3D stacks, ensuring the uniformity and integrity of these dielectric and passivation layers is essential for electrical performance and reliability. As Leray notes, addressing future challenges "will require innovation and synergistic integration of different technologies." This JDP is designed to do just that, creating a workflow where fast optical inspection identifies areas of interest, and high-resolution AFM performs the deep-dive analysis.

A Partnership Forged at the Cutting Edge

The choice of imec as a partner is a strategic masterstroke. Based in Belgium, imec operates at the absolute frontier of semiconductor R&D, bringing together rivals and partners—from chip designers to equipment makers—to collaboratively solve the industry's grand challenges. By becoming a member of imec's Industrial Affiliation Program (IIAP) on 3D Systems Integration and providing its tools for evaluation, Park Systems is effectively beta-testing its technology on the chip designs of tomorrow.

Imec will provide samples based on its next-generation 3D packaging and logic roadmaps, giving Park Systems direct access to the very structures that the rest of the industry will be struggling to manufacture in three to five years. This deep collaboration, building on previous JDPs signed in 2015 and 2020, allows the company to refine its hardware and software for real-world, cutting-edge applications, ensuring its solutions are not just theoretically sound but production-ready when the market needs them. For Park Systems, the validation that comes from being an essential partner in imec’s ecosystem is invaluable, elevating its standing against larger, more diversified competitors like KLA and Applied Materials.

Building a Future in Concrete and Silicon

The JDP announcement's timing with the inauguration of Park Systems' new global headquarters in Gwacheon, South Korea, is no coincidence. The state-of-the-art facility is more than a corporate milestone; it is the physical manifestation of the company's strategic ambitions. Described as a facility "designed to advance the capabilities this collaboration aims to explore," the headquarters will serve as an R&D and collaboration hub, strengthening the company's ability to innovate and support complex global partnerships like the one with imec.

This investment signals a broader strategic shift. Park Systems is leveraging its deep roots in AFM to build a comprehensive metrology platform, positioning itself as an indispensable partner for the high-growth 3D integration market. "Semiconductor manufacturing has entered a new era of complexity — one that places ever-greater demands on metrology," said Dr. Sang-il Park, Founder and CEO of Park Systems. "This JDP with imec deploys the full suite of our new metrology solutions to address the challenges that will define the next generation of semiconductor manufacturing."

By proactively developing the tools to measure the future, Park Systems is not just keeping pace with the semiconductor industry's evolution—it is actively enabling it. This strategic focus on solving tomorrow's problems today demonstrates a clear understanding that in the intricate, high-stakes world of advanced semiconductors, the ability to see and measure with precision is the ultimate competitive advantage.